Release v0.1.0

Date: 2026-07-03 · Milestones completed: M0 (bootstrap), M1 (core + CPU detection + dispatch), M2 (testkit + bench harness), M3 (Tier A scalar kernels). Release template per REQ-DOC-010.

Summary

The first tagged release: all six Tier A kernel families — K1 compare, K2 filter, K3 sel_convert, K4 mask_algebra, K5 take/dict_decode, K6 reduce/SMA — implemented as readable scalar reference specifications behind the runtime-dispatch framework, with the complete contract surface (Surface B vocabulary types, Surface C dispatch/introspection), dual-oracle test stack (71 tests: unit, property, differential-vs-naive, invariant, guard-page, no-allocation), validated benchmarks, and CI across x86-64/ARM64/macOS with ASan/UBSan/TSan.

Completed requirements

All requirement IDs allocated to M0–M3 per PRD 01 §6 / 18; per-milestone lists in the gate records (M0, M1, M2, M3).

API changes

Initial public surface (0.x-fluid until v1.0): quiver/core.h, quiver/dispatch.h, and the six Tier A family headers. 176 concrete dispatched symbols behind template facades (ADR-006).

Benchmark / ledger changes

Family + dispatch-overhead benchmarks exist and validate before timing (REQ-BENCH-004). No ledger yet and therefore no published performance numbers (Charter T2): the first ledger publication is v0.3 (M5).

ADR changes

None (all 26 remain Accepted; ADR-013 realized with the scalar strict-fold recourse).

Known limitations

Scalar backends only — explicit SIMD lands at M4 (AVX2), M5 (NEON), M7 (AVX-512). No install/package/amalgamation until M8 (consume via add_subdirectory/FetchContent). Tier B families (hash, unpack, arith, arith_guarded) arrive at M6. Real-PMU benchmark evidence deferred to registered ledger machines (M5). MSVC remains tier-2 best-effort.

Migration notes

None (first release).