Release v0.5.0 — AVX-512 tier

Date: 2026-07-04 · Milestone completed: M7 (AVX-512 across the kernel families, with Intel SDE correctness coverage). Release template per REQ-DOC-010. Gate record: gates/M7.md.

Summary

The fourth ISA tier. Native AVX-512 backends for the seven families where a distinct technique wins over AVX2 — K1 compare (opmask predicates), K2 filter / K3 select (vpcompress to register), K4 mask, K7 hash (native vpmullq), K8 unpack (512-bit widening), K9 arith. K5 take, K6 reduce, and K10 arith_guarded run the AVX2 backend on AVX-512 hardware (no measurable win to justify a distinct backend without hardware). Correctness for the whole tier is proven under Intel SDE (-spr and -skx) in CI — there is no AVX-512 hardware to run on, so this is a correctness release, not a performance one.

Completed requirements

M7 allocation per PRD 18: REQ-SIMD-004 (required set F+BW+DQ+VL); REQ-CI-004 (SDE job, both profiles); REQ-TEST-017 (SDE suite execution); REQ-DISP-004/-011 (feature-gated tier + VBMI2 groundwork). Deferred (risk R-06, no AVX-512 hardware): the AVX-512 performance ledger; distinct AVX-512 backends for K5/K6/K10; the VBMI2 8/16-bit vpcompressb/w compaction path. Details and reopening criteria in the gate record.

API changes

None. On AVX-512 hardware (or under SDE) the dispatcher selects the AVX-512 backend for the seven native families; results are bit-identical to scalar (the frozen qhash64 and all integer kernels), with the documented float-reassociation policy unchanged.

Validation

Intel SDE is the AVX-512 correctness gate (ADR-010): there is no reliable local AVX-512 execution (QEMU emulates AVX-512 only partially; SDE cannot run under QEMU), so the sde-avx512 CI job runs the unit/differential/invariant suites under sde64 -spr and -skx, plus a sanitized differential leg under -spr (REQ-SIMD-003 masked-tail lowering). Dispatch selection is additionally proven locally via a compile-gated, release-excluded detection seam (QUIVER_TEST_FORCE_ISA). Every rollout PR was SDE-green.

ADR changes

ADR-010 (SDE-based AVX-512 coverage) realized. None amended. Two small proposed amendments are recorded in the gate (a compile-gated test-only detection seam for PRD 07; the SDE leg (b) scope for REQ-CI-004).

Known limitations

No AVX-512 performance numbers — no registered AVX-512 machine (R-06; the ledger stays at one secondary µarch, Apple M2). K5/K6/K10 have no distinct AVX-512 backend (they fall through to AVX2, correct and SDE-tested); VBMI2 8/16-bit compaction is deferred. All are hardware-gated follow-ups, not correctness gaps. Packaging/amalgamation lands at M8.

Migration notes

None required — purely additive.