Release v0.4.0 — Tier B kernel families

Date: 2026-07-03 · Milestone completed: M6 (Tier B families K7–K10, scalar + AVX2 + NEON). Release template per REQ-DOC-010. Gate record: gates/M6.md.

Summary

The kernel catalog is now complete on the first three tiers: K7 hash (frozen qhash64 with committed cross-platform golden vectors), K8 unpack (bit-unpacking with frame-of-reference fusion over an untrusted input, exact read bound), K9 arith (wrapping/IEEE elementwise arithmetic), and K10 arith_guarded (overflow-checked and saturating arithmetic — never silent UB). The evidence-gated K7 NEON technique is decided from measured data on registered hardware.

Completed requirements

M6 allocation per PRD 18: REQ-K7-001..004; REQ-K8-001..004; REQ-K9-001..002; REQ-K10-001..003; REQ-TEST-015, -016; REQ-SEC-004; REQ-KERNEL-007 (K7 NEON leg — GPR chain ships, measured). REQ-LEDGER-012's ≥2-machine coverage remains an open deferral (one registered machine — Apple M2, secondary platform); details and reopening criteria in the gate record.

API changes

New public surface: quiver/hash.h (hash64, hash64_combine), quiver/unpack.h (unpack, unpack_for), quiver/arith.h (arith, arith_checked, arith_saturating). The umbrella quiver/quiver.h now includes them. No changes to existing Tier A APIs.

Behavior notes

• qhash64 output is frozen (ADR-012): bit-identical across x86/ARM/macOS and stable per major version; changing constants or rounds is a v2 event. Non-cryptographic by contract.
• Integer arith wraps (two's-complement/modular); floats are native IEEE-754. NaN arithmetic results are reproducible as a class (NaN-ness), not bit-exact — IEEE does not pin NaN-payload propagation and the charter forbids fast-math.
• On ARM64 the shipped K7 backend is the GPR fmix64 chain (the vector decomposition loses ~1.3× on Apple M2 — K7 NEON investigation).

Benchmark / ledger changes

First committed Tier B ledger results under ledger/results/apple-m2/ (seven zero-deviation run directories at this commit; n=65536, covering the bit_width and overflow_density axes). Variant vocabulary on ARM: neon vs autovec (REQ-BENCH-010). Verdict blocks with entry-id references live on all three family pages (REQ-LEDGER-011). Verdicts: K7 hash parity 1.00×; K8 unpack 12.8×–42.4× for byte-aligned widths and ~1.07–1.10× (delegated) otherwise; K9 arith a published loss ~0.90× (the autovectorizer wins pure streaming arithmetic); K10 arith_checked 1.42× (flat across overflow density) and arith_saturating 1.65×. Apple Silicon entries are secondary-platform and carry no PMU counters (REQ-LEDGER-008); the ≥2-µarch coverage gate remains an open deferral.

ADR changes

ADR-012 (qhash64 v1), ADR-014 (overflow reporting), ADR-026 (bit-packing layout) realized. None amended.

Known limitations

Ledger coverage is one µarch (Apple M2, secondary; no PMU counters) — primary-platform x86 entries await registered hardware; no numbers are invented (Charter T2/T7). K8 sub-byte SIMD widths delegate to the scalar core (byte-aligned widths are vectorized); 64-bit checked/ saturating multiply is scalar (REQ-K10-003). AVX-512 lands at M7, packaging at M8.

Migration notes

None required — purely additive.