Gate record — M5: Tier A NEON + Ledger v1 → v0.3 (public launch)

Date: 2026-07-03 · Milestone: M5 (PRD 18 §M5) · Decision: PASS with one open coverage deferral (§7-D1: REQ-LEDGER-012 three-µarch gate — one registered machine exists; no data invented).

1. Objective

NEON parity for the six Tier A families (Charter T5 launch condition) and the ledger as a product: schemas, reproducible runner, machine registry, committed results, and explicit-vs-autovec verdicts on every family page.

2. Files created / modified

Created: src/kernels/{compare,filter,select,mask,take,reduce}/<f>_neon.cpp ×6; NEON TBL control tables in MOD-KCOMMON (kCompactNib8/16/32, kCompactPair64); tests/unit/test_luts.cpp (runtime re-derivation of all seven LUTs — closing a REQ-SIMD-005 clause that had gone untested since M3); bench/baselines/baseline_neon.cpp (the ARM identity, REQ-BENCH-010); ledger/schema/{ledger-entry,manifest}.schema.json (QLS-1); ledger/runner/quiver_ledger.py + qledger/{stats,schema_check,environment, gbench}.py + runner/tests/ (golden statistics + schema accept/reject fixtures, wired into ctest); ledger/machines/apple-m2-mba.json; ledger/results/apple-m2/<run>/ (entries + raw + manifest); ledger/README.md; docs/guides/disputes.md; docs/releases/v0.3.0.md; this record.

Modified: src/dispatch/dispatch_tables.cpp (NEON declarations; row slot [1]); CMakeLists.txt (NEON TUs; C++20 module scanning disabled — no modules, and clang-scan-deps is absent from minimal environments); bench/harness/bench_common.h (variant_name: platform-dependent vocabulary — ARM reports the scalar build as autovec, REQ-BENCH-002/-010) + all six family benches; bench/micro/bench_reduce.cpp (f64 policy recompute parameterized by effective backend width); tests' float-sum policy maps (NEON {w=4/2, a=4}); .github/scripts/repo_lint.py (qle:<entry_id> docs check, REQ-LEDGER-015) + manifest (state M5; ledger/ unfrozen); .github/workflows/nightly.yml (M6 avalanche placeholder note); docs/benchmarks/methodology.md (QLM-1 complete); docs/api/*.md ×6 (NEON notes + verdict blocks); docs/internals/kernel-common.md; CHANGELOG.md; mkdocs nav.

3. Requirements satisfied

• REQ-SIMD-008 — ≥4 independent 128-bit ops in flight where throughput-critical (K4 explicit 4× unroll; K6 A=4 accumulators; benchmark-evidence requirement, not a hard gate).
• REQ-INT-004 — runner is Python ≥3.11, stdlib only.
• REQ-LEDGER-001..011, -013..015 (Tier A scope): QLS-1 schemas + structural validation in ctest; normative entry/manifest fields; ADR-020 statistics with golden tests; CV policy enforced (>5% excluded, 3–5% flagged); fresh-process shuffled repetitions with recorded seeds; registered-machines-only; Apple flags + no cycles_per_value; reproduction command documented (dispute guide); append-only results; verdict blocks on all six family pages incl. losses; environment checklist rejects dirty trees/wrong governor; QLM-1 versioned and documented; docs reference entries via qle: ids, checked by lint.
• REQ-BENCH-010 — ARM autovec identity implemented via variant naming (the portable scalar build IS the NEON baseline; no separate scalar variant on ARM).
• REQ-BENCH-011/-014 — regression-subset machinery available via --filter (first release-over-release comparison possible from v0.4, since v0.3 is the first ledger); flamegraph script shipped at M2, investigation-dir convention documented.
• REQ-KERNEL-007 / REQ-K5-004 (NEON leg) — recorded N/A: NEON has no gather; rationale on the family page.
• REQ-DOC-007 — verdict blocks + entry-id existence check live.

4. ADRs realized

ADR-020 (seeded percentile bootstrap, B=10,000, first-party ~80-line implementation with golden fixtures); ADR-021 (append-only per-run directories, schema-validated JSON via PR). ADR-013 realized on NEON with the frozen combine; ADR-003/015/016/023/025 exercised by the new backends.

5. Tests / benchmarks / docs added

test_luts.cpp (7 LUT re-derivations); ledger runner unit tests (8 statistics + 10 schema) + Ledger.ResultsValidate over committed results — 81 ctest targets green natively. ARM64 Linux container: 74/74 under ASan+UBSan; ≥20 s/family differential fuzzing against NEON, clean (~1M+ execs/family). Docs: NEON per-ISA notes ×6, verdict blocks ×6, QLM-1 completion, ledger README, dispute guide, kernel-common table update.

6. Ledger run (the v0.3 data)

Two publishable run directories on apple-m2-mba (both zero-deviation manifests):

• 20260703-4ec273e2904d — the full Tier A grid (122 configurations × 10 fresh-process repetitions, 1 s timing windows): 50 published (26 clean, 24 in the 3–5% noisy band), 72 excluded at CV > 5% per REQ-LEDGER-005.
• 20260703-4ec273e2904d-b — supplementary run for the classes the noise excluded (mask, take, f64 sums; 20 configurations, 2 s windows): 20/20 published, 0 excluded — longer windows keep processes in P-core steady state on this fanless machine.

Some verdict pairs match a -b entry with a main-run entry (same machine, same commit, different window lengths — both CV-screened; ns_per_batch medians are window-length independent). Noise reality of this hardware, recorded honestly: macOS offers no core pinning or governor control, so short-window classes exceed the CV policy easily; the 72 exclusions are listed in rejected_noisy.json and rerunnable per the disputes guide.

Verdicts (REQ-LEDGER-011, neon vs autovec, geomean over published pairs):

family	verdict
K1 compare	LOSS 0.69× — autovec wins the measured i64 shapes (three bit-exact packing iterations later; the pledge's documented-loss acceptance item)
K2 filter	win 1.72× (6 pairs)
K3 sel_convert	win 7.59× (2 pairs)
K4 mask_algebra	parity 0.97× (the Survey §4.4 predicted honest verdict)
K5 take	parity 1.00× (delegation by design — no gather on NEON)
K6 reduce	win 4.43× (f64 blocked sums ~8× vs the strict baseline — ADR-013 caveat stated on the page)

First-ledger evidence drove two shipped fixes before publication: the K6 integer-sum unroll (REQ-SIMD-008; 4× loss → parity at the memory ceiling, masked path wins 5.6×) and the K1 packing rework (0.39× → 0.69×; residual loss published). Follow-up recorded on the compare page: delegating wide-lane compares to the scalar core on ARM is an evidence-gated option for v0.4.

Reproduction dry run (REQ-LEDGER-009 / PRD 11 §10): PASS. Fresh clone of the branch → cmake --preset bench build → quiver_ledger.py run --machine apple-m2-mba --filter 'BM_filter/bitmap/(neon|autovec)/i64/n=65536/sel=90/pat=uniform' (10 reps, 1 s windows). Both variants reproduced within the committed entries' 95% CIs: neon median 23513 ns vs committed 23247 ns CI [22974, 23945] (+1.1%); autovec 40190 ns vs 40369 ns CI [39748, 40707] (−0.4%); CIs overlap in both directions.

7. Checks: passed / failed / deferred

Passed: dev ctest 81/81 (NEON exercised natively by every suite); -Werror build; bench builds + validation under both ARM tiers; repo lint (incl. the new entry-id check); mkdocs strict; clang-format (18.1.8); ARM64 container ASan+UBSan suite + fuzzing; runner golden/statistics/schema tests; quiver_ledger.py validate over the committed run.

Deferred: - D1 (open, milestone-level): REQ-LEDGER-012 three-µarch coverage. The registry holds ONE machine (Apple M2 — a secondary platform by charter definition). The Zen 4/5 and Golden-Cove machines named by the PRD do not exist in this project's physical inventory; no CI runner may substitute (REQ-LEDGER-007), and no number is invented (Charter T2). Reopen: on first registered x86 hardware, run the full Tier A grid + the M4-deferred K5 gather and selectivity-flatness protocols. Until then the ledger publishes what it can prove: one µarch, honestly labeled (ledger README carries the caveat prominently). - D2: PMU-based cycles_per_value — absent on Apple by design (REQ-LEDGER-008); arrives with the first Linux x86 registered machine. - CI matrix legs: GitHub-side, discharged by the PR checks.

Failed: none outstanding.

8. Ambiguities and deviations

• A1 (interpretation): REQ-LEDGER-002 lists ONE ci95_lo/ci95_hi pair per metric while ADR-020 computes CIs for both median and min. Implemented: the CI pair reports the median estimator (the headline statistic); min is a point estimate. Proposed smallest amendment: REQ-LEDGER-002 append "(CI pair reports the median estimator)".
• A2 (interpretation): REQ-SIMD-005's NEON tables are worded "16-entry × 8-byte"; 32/64-bit lanes need 16-byte TBL controls. Implemented 8-byte controls for 8/16-bit lanes and 16-byte for 32/64-bit (kCompactNib32, kCompactPair64) — the intent (nibble TBL tables within the LUT budget) is preserved; total budget remains ≪ 16 KiB.
• D1 (technique note): K1 NEON packs predicate bits via bit-weight AND + vaddv rather than the PRD's shrn narrowing idiom — semantically identical output; shrn is recorded as the alternative to evaluate against ledger evidence.
• D2 (scope note): quiver_bench_dispatch is excluded from ledger runs: its third name segment is a dispatch MODE (dispatched/direct), not a QLS-1 kernel variant.
• D3 (provenance note): the run's bench binaries were built from the tree one runner-only commit before the recorded HEAD; library and bench sources are byte-identical between the two commits.
• D4: REQ-BENCH-011's release-over-release regression comparison has no baseline at v0.3 (first ledger release) — first executable at v0.4.

9. Scope exclusions

Tier B families (M6), AVX-512 (M7), packaging/amalgamation (M8), representation study (M9). Graviton and ≥5-µarch coverage (M10, REQ-LEDGER-012 v1.0 clause).

10. Documentation rationale / debt

Verdict blocks cite committed entry ids only (lint-enforced). Debt: verdicts exist for one µarch — pages say so explicitly; x86 verdict columns appear with hardware. The shrn-vs-vaddv K1 note and the M4 investigation remain open evidence items.

11. Final gate decision

PASS with the §7-D1 coverage deferral recorded as open. All buildable, testable, and documentable M5 deliverables exist and are validated; the ledger publishes exactly what was measured on registered hardware and nothing else. Charter §9.3 shrink-point note: the repository state at v0.3 is certified releasable-as-final — the project could stop here and remain a coherent, honest artifact. Gate+ actions after merge: tag v0.3.0, publish the release, record the public-launch checklist (naming diligence confirmed at Charter §1 gate — done in the charter itself).