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Gate record — M3 (Tier A scalar kernels, K1–K6) → v0.1

  • Milestone: M3 per docs/prd/18-milestones.md
  • Objective: the six Tier A families, scalar backends, full contract enforcement, complete family test/bench/doc scaffolding.
  • Date: 2026-07-03
  • Recorded per: REQ-MS-002
  • Result: PASS (deferrals in §7)

1. Files created

Public surface: include/quiver/{compare,filter,select,mask,take,reduce}.h. Shared kernel layer: src/kernels/common/{kernel_common.h,target_regions.h,luts.h,luts.cpp}. Families ×6: <f>_scalar_impl.h (the semantic specifications, Charter T3) + <f>_scalar.cpp (176 concrete backends). Tests: 6 unit, 6 property, 6 differential, 5 invariant files (incl. the guard-page suite inv_guard_pages.cpp), tests/regression/README.md. Benchmarks: bench/micro/bench_{compare,filter,select,mask,take,reduce,dispatch}.cpp. CI: .github/workflows/nightly.yml. Docs: 6 family API pages, docs/guides/getting-started.md, docs/releases/v0.1.0.md, this record.

2. Files modified

include/quiver/detail/extern_decls.h (X-macro inventory: 176 entries driving declarations AND dispatch tables — consistency by construction, REQ-KERNEL-005), src/dispatch/dispatch_internal.h (typed constinit BackendRow<Fn> — see §9), src/dispatch/dispatch_tables.cpp (entries/rows/wrappers/warmup registry emitted from the X-macro), include/quiver/quiver.h, CMakeLists.txt, tests/CMakeLists.txt (suite executables per PRD 03 §4), tests/unit/test_dispatch.cpp (typed rows), testkit (generators.{h,cpp} guard-page buffers; reference.h family oracles), bench/CMakeLists.txt, .github/{repo-manifest.json,scripts/repo_lint.py} (own-family include rule), docs/mkdocs.yml, docs/architecture/module-map.md, README.md, CHANGELOG.md.

3. Requirements satisfied (PRD 18 M3 allocation)

REQ-KERNEL-001..006, -008 (Tier A); REQ-K1-001..003; REQ-K2-001..003; REQ-K3-001..002; REQ-K4-001..003; REQ-K5-001..003; REQ-K6-001..005; REQ-MEM-001..010; REQ-API-006, -008..012; REQ-SIMD-006, -009; REQ-TEST-003 (scalar tier), -005, -006, -008, -011, -013, -014; REQ-ERR-001, -003, -004, -006, -007; REQ-SEC-001..003, -005; REQ-BENCH-003, -009; REQ-DOC-002, -003 (six families), -006, -010..012; REQ-CI-006; REQ-REPO-003, -004, -010; REQ-REL-001, -003, -005, -006 (first tagged release).

4. ADRs realized

ADR-013 (float policy: scalar = strict left fold, the charter's strict-order recourse; policy oracle in testkit), ADR-015 (scalar tails trivially; per-ISA at M4+), ADR-016 (tail zeroing, invariant-tested), ADR-023 (aliasing allowlist, equivalence-tested), ADR-025 (selection semantics, sortedness invariant + debug-assert bounds scans).

5. Tests and benchmarks added

71 tests total (from 23): 6 family unit suites (hand-computed, IEEE float blocks, boundary values, participation/identities, checked-sum boundary overflow, in-place equivalence, vacuous truths); 6 property suites (representation equivalence, round-trip identities, De Morgan/idempotence/involution/popcount conservation, gather identities, fused ≡ composed, sum-over-selection ≡ filter-then-sum, checked-flag ≡ 128-bit reference); 6 differential suites (all host backends vs the naive oracle, byte-exact incl. strict-fold float oracle per REQ-TEST-004, over the L-set with QUIVER_NIGHTLY widening); invariant suites (tail-zeroing, determinism per ISA, selvec sortedness, no-allocation via global new/delete counters, guard pages at capacity boundaries both ends + the fused-decode untouched-codes proof). Benchmarks: 6 family + dispatch-overhead (dispatched vs direct symbol at n ∈ {1, 64, 4096}, warmup steady-state), every one validating against an independent recompute pre-timing (REQ-BENCH-004).

6. Commands run (local evidence)

# Command Result
1 dev/release/asan-ubsan/tsan presets + ctest 71/71 pass each; sanitizer-clean; 0 warnings
2 bench preset build + all 8 binaries with validation all validate and run; dispatch-overhead numbers observed locally (not published — no ledger yet, Charter T2)
3 clang++ -fsyntax-only -arch x86_64 over shipped TUs x86 preprocessor paths verified on this ARM host
4 uvx clang-format@18.1.8 --dry-run --Werror clean
5 python3 .github/scripts/repo_lint.py PASS (M3 manifest; own-family include rule added)
6 mkdocs build --strict run pre-PR; recorded in the PR

7. Checks deferred (with reasons)

  1. CI matrix + SDE-less AVX-512: the full matrix runs on this PR; AVX-512 code does not exist until M7, so no SDE dependency yet.
  2. Nightly workflow first execution (full sweep, MSan instrumented-libc++ build, coverage, -Rpass-missed) — scheduled post-merge; results reviewed at the M4 gate. The MSan libc++ build is cache-primed on first run.
  3. Real-PMU bench evidence — M5 registered machines (carried from M2 §7).

8. Scope exclusions

Tier B families (M6); AVX2/NEON/AVX-512 backends and bench/baselines/ (M4/M5/M7); fuzz targets (M4); ledger runner/results (M5); amalgamation/install/examples (M8).

9. PRD ambiguities and deviations

  1. Typed backend rows (implementation-level resolution). PRD 07 §4 sketches BackendRow { KernelFn backends[4] } (type-erased). reinterpret_cast of function pointers is not constexpr, so type-erased rows cannot be constinit-initialized (REQ-CORE-004 conflict). Resolution: BackendRow<Fn> typed by each entry's signature (constinit with no casts); erasure happens at runtime inside resolve/dispatch_get where the round-trip is well defined; DispatchEntry storage stays type-erased exactly as specified. The internal-structure sketch is implementation guidance, not public contract; REQ-DISP-007/-008 semantics unchanged. Documented in dispatch_internal.h; proposed smallest PRD edit: 07 §4 diagram note "rows are typed per entry; erasure at runtime".
  2. Guard-page suite location: PRD lists 4 invariant files + "guard-page suite in testkit"; realized as testkit GuardedBuffer + a fifth invariant file inv_guard_pages.cpp (the suite needs a test translation unit). Inventory-consistent in spirit; manifest updated.
  3. Concrete-symbol count: 176 (not the PRD 07 §8 "~300" estimate) — K5/K6 optional-selection overloads share concrete symbols via a nullable sel parameter, within ADR-006's "fewer where a concept narrows" latitude; the façade overload surface matches PRD 04 exactly.
  4. bench_dispatch declares one internal scalar symbol directly (the direct-call baseline the dispatch-overhead hypothesis requires); documented in-file as bench-only use of an unstable symbol.

10. Documentation

Six family pages (contract tables, scalar-reference pointers, per-ISA notes, ledger sections explicitly "pending v0.3" — no unpublished numbers), getting-started guide with a full pipeline example, nav/module-map/README/CHANGELOG, release notes v0.1.0. No debt.

11. Final gate decision

PASS conditional on this PR's CI matrix; v0.1.0 is tagged after the squash-merge (REQ-REL-001/-006: first release checklist executed manually per REQ-REL-003 — release.yml automation is an M8 deliverable).