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Gate record — M7: AVX-512 across all families → v0.5

Date: 2026-07-04 · Milestone: M7 (PRD 18 §M7) · Decision: PASS with recorded deviations (§8: three families fall through to AVX2; VBMI2 8/16-bit compaction and the AVX-512 performance ledger are hardware-gated deferrals — R-06).

M7 was implemented as a validation slice first, then the backend rollout (a deliberate de-risking split, §2): prove the AVX-512 dispatch + correctness path with one backend before writing the rest. The rollout then shipped native AVX-512 backends for the seven families where a distinct technique wins over AVX2, one per PR, each proven under Intel SDE:

PR family technique
#8 K4 mask 512-bit bitwise (the validation slice)
#9 K1 compare native opmask predicates (_mm512_cmp_*_mask)
#10 K7 hash native vpmullq (vs AVX2 3×vpmuludq)
#11 K8 unpack 512-bit widening loads (vpmovzx)
#12 K9 arith vertical add/sub/mul, native vpmullq
#13 K2 filter / K3 select native vpcompress to register (Zen-4-safe)

K5 take, K6 reduce, and K10 arith_guarded fall through to the AVX2 backend on AVX-512 hardware (§8) — no distinct AVX-512 technique wins without measurement, and the AVX2 code is correct and SDE-tested under the avx512 cap.

1. Objective

The fourth ISA tier (AVX-512) across all ten kernel families, with correctness coverage by Intel SDE (no AVX-512 hardware is available); VBMI2/VPOPCNTDQ handled as resolution-time sub-features (REQ-DISP-011). M7.0 objective: prove public API → dispatch resolver → AVX-512 row (slot [3]) → AVX-512 backend is selectable, executable, and differentially tested, and settle the local vs CI validation seam.

2. Validation approach — DECISION (empirically grounded)

Decision: Intel SDE in CI is the AVX-512 correctness gate; a small test-only detection seam proves dispatch selection locally. There is no reliable local AVX-512 execution environment on the project's ARM host.

Evidence gathered building the slice (host: Apple M2, ARM64):

  • SDE cannot run under QEMU. Intel SDE (Pin-based) refuses to instrument a process being emulated by QEMU-user (Could not instrument process ... expected binary for the Intel(R) 64 architecture). So SDE is a CI-only tool (GitHub x86 runners), exactly as ADR-010 intends.
  • QEMU does not reliably execute AVX-512. The Docker linux/amd64 QEMU emulates some AVX-512F (_mm512_add_epi64 runs) but SIGILLs on others (_mm512_and_si512 / vmovdqu64), at both -O0 and -O2. So compiling AVX-512 locally works, but executing arbitrary AVX-512 kernels does not.
  • Dispatch selection IS locally provable. With the seam (QUIVER_TEST_FORCE_ISA=avx512, compiled only into tests-enabled builds), cpu_supports(kAvx512), set_isa_override(kAvx512), and active_isa()==kAvx512 all resolve correctly under QEMU — because resolution is arch-independent logic that does not execute a kernel. Verified by a standalone probe and by the DispatchAvx512.TierSelectableIffFeatureBitsPresent unit test (negative branch on any host without the feature bits; positive under the seam or real/SDE AVX-512).

Ranking realized (per the plan): SDE CI + small detection seam (preferred) — SDE proves kernel-output correctness (leg (a) -spr/-skx, leg (b) sanitized -spr; the differential suite auto-covers AVX-512 because SDE reports real AVX-512 CPUID), and the seam gives local dispatch-selection coverage. Direct-call QEMU harnesses were rejected (same SIGILL; and they would not prove dispatch anyway). The seam is test-only (compiled out of any tests-off/release/ install build, so shipped detection stays pure CPUID, PRD 07) — recorded as a deviation in §8.

3. Files created / modified (M7.0 slice)

Created: src/kernels/mask/mask_avx512.cpp (K4 — the first AVX-512 backend); this record.

Modified: src/kernels/common/target_regions.h (narrowed QUIVER_TARGET_AVX512_BEGIN to the required set F+BW+DQ+VL; added QUIVER_TARGET_AVX512_VBMI2_* for later sub-feature variants; a token-built pragma so clang-format cannot split the target string into two literals — the reason the previously-unused macro was latent-broken); src/dispatch/dispatch_tables.cpp (AVX-512 declarations + incremental slot-[3] wiring via per-uid markers — only K4 wired, the rest fall through to AVX2); src/cpu/cpu_features.cpp (test-only detection seam); CMakeLists.txt (QUIVER_AVX512_SOURCES; QUIVER_TEST_SEAMS define on tests-enabled builds); .github/workflows/ci.yml (the SDE AVX-512 job, REQ-CI-004); tests/unit/test_dispatch.cpp (DispatchAvx512 selectability test); docs/api/mask.md (AVX-512 note).

4. Requirements satisfied (M7.0)

  • REQ-SIMD-004 — base required set F+BW+DQ+VL enforced by the narrowed target region; K4 uses only that set (correct on -skx).
  • REQ-CI-004 — SDE job added (download cached pinned SDE; leg (a) release suites under -spr and -skx; leg (b) sanitized suites under -spr).
  • REQ-DISP-004 — AVX-512 tier selectable iff the feature bits are present (unit test).
  • REQ-DISP-011 (groundwork) — VBMI2 region exists for resolution-time variants; exercised when K2/K3 land.
  • REQ-TEST-017 — SDE suite execution wired (proven green in CI on this PR).

5. Tests / benchmarks / docs added (M7.0)

DispatchAvx512.TierSelectableIffFeatureBitsPresent (dispatch selection, both branches); the existing differential suite auto-covers the K4 AVX-512 backend under SDE; docs/api/mask.md AVX-512 note. No benchmarks (no AVX-512 hardware → no ledger; performance is out of SDE scope, ADR-010 — the R-06 hardware deferral stands).

6. Commands run

  • Native (ARM) cmake --build --preset dev + ctest --preset dev → 123/123.
  • x86 container (--platform linux/amd64, clang-18): configure/build dev; probe shows active_isa=avx2 without the seam and active_isa=avx512 with it; clang-format-18 clean.
  • SDE feasibility empirically established (see §2).
  • SDE correctness legs run in CI (this PR's sde-avx512 job).

7. Checks: passed / failed / deferred

Passed: native dev 123/123 on every rollout PR; x86 dispatch-selection probe + seam; clang-format-18; clang-tidy-18; full build matrix; the sde-avx512 job green on every PR (K1/K2/K3/K4/K7/K8/K9 native AVX-512 backends executed under -spr and -skx; K5/K6/K10 exercised as the AVX2 fall-through under the avx512 cap). Deferred: AVX-512 ledger/performance (no registered AVX-512 machine — risk R-06); distinct AVX-512 backends for K5/K6/K10 and VBMI2 8/16-bit compaction (§8, hardware-gated).

8. Ambiguities / deviations

  • Detection seam (deviation, test-only): PRD 07 specifies pure-CPUID detection. QUIVER_TEST_FORCE_ISA is compiled only into tests-enabled builds (QUIVER_TEST_SEAMS), never into release/install artifacts, so shipped detection is unchanged. It exists solely because no local AVX-512 execution environment exists (§2) and dispatch-selection still needs local test coverage. Proposed smallest amendment: PRD 07 append a note permitting a compile-gated test-only detection override for CI-less dispatch validation.

  • SDE leg (b) scope (deviation from REQ-CI-004 "unit + differential"): leg (b) runs the differential suite only. It is the sanitized masked-tail coverage leg (b) uniquely provides (REQ-SIMD-003) and is fork-free; the unit and invariant suites get full SDE coverage in leg (a). Running unit (death tests) or invariant (guard-page) under ASan+SDE hangs — their forks do not terminate under Pin-style emulation (observed as a 6 h orphan-process cancel). Proposed smallest amendment: REQ-CI-004 leg (b) → "differential (the sanitized masked-tail leg); fork-based suites run only in leg (a)."

  • Three families fall through to AVX2 (deviation from "×10 AVX-512 TUs"): K5 take, K6 reduce, and K10 arith_guarded keep slot [3] empty and resolve to the AVX2 backend on AVX-512 hardware. Rationale: no distinct AVX-512 technique wins over AVX2 for them without measurement, and there is no AVX-512 hardware to measure (R-06) — K5's gather is evidence-gated (AVX2/NEON already delegate), K10's checked add/sub are already vectorized in the AVX2 backend, and K6's blocked float sums run bit-identically as the AVX2 fall-through (so the ADR-013 per-backend float-sum oracle needs no avx512 remap — the concern noted at M6 is moot). All three are correct and SDE-tested under the avx512 cap. Proposed smallest amendment: PRD 18 §M7 — "distinct AVX-512 backends are written where a technique wins over AVX2; families with no measurable win fall through to AVX2 until AVX-512 hardware is registered (R-06)."

  • VBMI2 8/16-bit compaction deferred: K2/K3 native compaction covers 32/64-bit lanes (vpcompressd/q, base set). The 8/16-bit vpcompressb/w path needs VBMI2 as a resolution-time variant (REQ-DISP-011); it is a hardware-gated follow-up (those widths fall through to AVX2). The VBMI2 target region exists in target_regions.h for when it lands.

9. Scope exclusions

Non-AVX-512 work; SQL/parser/planner/engine behavior; performance claims without registered hardware. Distinct AVX-512 backends for K5/K6/K10 and the VBMI2 8/16-bit compaction path (deferred to AVX-512-hardware availability, §8).

10. Documentation rationale / debt

All seven native-backend family pages (docs/api/{compare,filter,select,mask,hash,unpack, arith}.md) carry their AVX-512 notes; K5/K6/K10 pages keep the AVX2-fall-through posture (their AVX-512 rows note the hardware-gated deferral where relevant). The validation decision (§2) is recorded once so the rollout did not re-litigate it. Debt: distinct AVX-512 backends for K5/K6/K10 + VBMI2 8/16-bit compaction + AVX-512 ledger — all R-06 (no hardware).

11. Final gate decision

PASS with the §8 deviations recorded (three AVX2 fall-through families; VBMI2 8/16-bit and the AVX-512 performance ledger deferred to registered hardware — R-06). The AVX-512 tier's INTENT is met: every family runs correctly and is SDE-tested under the avx512 cap (-spr and -skx), with native AVX-512 techniques where they win over AVX2 and honest fall-through where they do not; no performance number is invented. Gate+ after merge: tag v0.5.0.