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Gate record — M9: Representation study, ledger expansion, paper

Date: 2026-07-05 · Milestone: M9 (PRD 18 §M9) · Decision: PARTIAL / DEFERRED. The hardware-independent deliverables are complete (the pre-registered representation study, its measurement instrument, and a one-ISA indicative slice); the acceptance criteria that require registered multi-µarch hardware (≥3 ISAs, ≥5 µarchs of entry-referenced ledger data) and an external workshop-paper draft are explicitly deferred under risk R-06 / REQ-LEDGER-012. No version tag (none required for M9). No performance data was invented (Charter T2).

1. Objective

The bitmap-vs-selvec representation study (Charter §6.2 / Survey §11.3 #3), ledger expansion to ≥5 µarchs, and a workshop-paper draft.

2. What was delivered (hardware-independent)

  • Pre-registered study under docs/benchmarks/investigations/representation-study/: the question + hypotheses (H1 bitmap flat; H2 selvec selectivity-dependence is ISA-dependent; H3 crossover), a method with a decision rule registered before cross-µarch data, the data file, an analysis of the available slice, and an OPEN conclusion. Same no-invented-data discipline as the k5-gather investigation.
  • Measurement instrument: bench_compare now registers both output forms of the same K1 predicate (bitmap_gt and selvec_gt) over identical input, each self-validating pre-timing (REQ-BENCH-004). Within the current QLM (no REQ-LEDGER-014 bump).
  • One-ISA indicative slice (apple-m2 / NEON, n=65536, sel ∈ {1,10,50,90,99}): confirms H1 (bitmap flat, ≤1% spread) and characterizes one point of H2 (NEON selvec is also flat — the full-vector-store compaction core — with a flat ~9% producer penalty vs bitmap, no producer-side crossover on this µarch). Graded honestly as an indicative bench run, not a CV-gated ledger publication (the session machine was not pinned-quiet); it carries no qle: id.

3. Deferred (hardware / external — R-06)

  • ≥3-ISA / ≥5-µarch entry-referenced ledger data. Only apple-m2-mba is registered. The full study (and thus the cross-µarch analysis, the crossover s*, and the conclusion) needs x86 (AVX2, AVX-512 if present) and a Graviton-class ARM part. Carried since M5 (REQ-LEDGER-012).
  • Workshop-paper draft (DaMoN/ADMS, Charter §9.1). External to the repo; the gate records the link when it exists. Depends on the multi-µarch data.

4. Acceptance status

The M9 acceptance ("answers the question with entry-referenced data across ≥3 ISAs and ≥5 selectivity points; paper draft exists") is not met and cannot be met without registered hardware: the ≥5 selectivity points are covered on one ISA, but ≥3 ISAs and the paper are blocked. Recorded as a deferral, not a pass — the honest state per the user directive (max honest progress).

5. Files

Created: docs/benchmarks/investigations/representation-study/{README,question,method,entries,analysis,conclusion}.md. Modified: bench/micro/bench_compare.cpp (selvec_gt measurement); docs/mkdocs.yml; manifest.

6. Checks

Hardware-independent gates green (build, bench_compare validates both forms, repo_lint, mkdocs --strict, format). Multi-µarch ledger regeneration: deferred (R-06).

7. Reopening

Registered access to ≥3 ISAs across ≥5 µarchs → run quiver_ledger.py run --machine <id> --filter compare per µarch, add qle:-referenced entries, evaluate the pre-registered decision rule, draw the conclusion, and complete the paper. Tracked under R-06 / REQ-LEDGER-012 (owned by M10).