Release v0.2.0

Date: 2026-07-03 · Milestone completed: M4 (Tier A AVX2). Release template per REQ-DOC-010. Gate record: gates/M4.md.

Summary

First explicit-SIMD tier: AVX2 backends for all six Tier A families, selected at runtime on AVX2+BMI2 x86-64 CPUs and proven bit-identical to the scalar references by the differential matrix, guard-page suite, and a new differential-fuzzing stack (six libFuzzer targets, cross-backend equality under ASan+UBSan). Equal-ISA auto-vectorized baselines (autovec-avx2) are built and benchmarked alongside the explicit variants (ADR-011) — still with no published performance numbers until the ledger launches at v0.3 (Charter T2).

Completed requirements

M4 allocation per PRD 18: REQ-SIMD-001..003/-005/-007, REQ-TEST-004/-007/-009 (+ REQ-TEST-011 regression activation), REQ-BENCH-006/-010, REQ-KERNEL-007 + REQ-K5-004 (decision recorded, evidence hardware-deferred), REQ-CI-005. Details and two documented deferrals in the gate record.

API changes

No signature changes. Behavior fix: an empty selection (SelVec{nullptr, 0}) now correctly means "select nothing" in the K5/K6 SelVec overloads; previously it was misread as "no selection" (dense) — memory-unsafe in fused dict_decode. Found by differential fuzzing; regression-locked. The avx2 dispatch tier now additionally requires BMI2 (correctness guard; every mainstream AVX2 CPU qualifies).

Benchmark / ledger changes

autovec-avx2 variants registered for every family microbenchmark (verdict pairs for the future ledger, REQ-BENCH-002); f64 sum validation is policy-aware (ADR-013). No ledger yet: first publication is v0.3 (M5).

ADR changes

None in status; ADR-003/ADR-011 realized; ADR-013 realized on AVX2 with its frozen combine order. One amendment proposed at the gate (NaN sum payloads compare as a class — test-oracle clarification, no kernel behavior change).

Known limitations

NEON lands at M5 (v0.3), AVX-512 at M7, Tier B families at M6. K5 gather-vs-scalar evidence awaits registered x86 hardware (default: scalar, held by survey prior — investigation). Float-sum results differ across ISAs by documented policy (strict scalar fold vs blocked SIMD accumulation); NaN sum payloads are unspecified. No install/package/amalgamation until M8.

Migration notes

None required. Code that (incorrectly) relied on an empty SelVec meaning "everything" must pass the no-selection overloads instead.