Release v0.3.0 — public launch

Date: 2026-07-03 · Milestone completed: M5 (Tier A NEON + Ledger v1). Release template per REQ-DOC-010. Gate record: gates/M5.md. This is the charter's 9-month shrink point: the repository state is certified releasable-as-final (Charter §9.3; shrink-point note in the gate record).

Summary

NEON backends for all six Tier A families (Charter T5 launch condition: scalar + AVX2 + NEON co-equal), and the performance ledger as a product: QLS-1 schemas, the stdlib-only reproducible runner (seeded bootstrap statistics, fresh-process shuffled repetitions, environment manifests, append-only results), the machine registry, and the first committed ledger run with explicit-vs-autovec verdicts on every Tier A family page — wins and losses alike (REQ-LEDGER-011).

Completed requirements

M5 allocation per PRD 18: REQ-SIMD-008; REQ-INT-004; REQ-LEDGER-001..011, -013..015 (Tier A scope); REQ-BENCH-011, -014 groundwork; REQ-DOC-007; REQ-KERNEL-007 K5-NEON leg (N/A — no gather on NEON, rationale on the family page). REQ-LEDGER-012's three-µarch coverage is an open deferral — one registered machine exists (Apple M2, secondary platform); details and reopening criteria in the gate record.

API changes

None. Behavior note: on ARM64 hosts the dispatcher now selects NEON backends by default (previously scalar); results are bit-identical except dense float sums, which follow the documented ADR-013 blocked policy (f32 {w=4, a=4}, f64 {w=2, a=4}).

Benchmark / ledger changes

First committed ledger results under ledger/results/apple-m2/. Variant vocabulary on ARM: neon vs autovec (the portable scalar build — no separate scalar variant exists on ARM, REQ-BENCH-010). Verdict blocks live on all six family pages, referenced by entry_id and checked at lint time (REQ-LEDGER-015). Apple Silicon entries are secondary-platform and carry no PMU counters (REQ-LEDGER-008).

ADR changes

ADR-020 (statistics) and ADR-021 (data model/storage) realized. None amended.

Known limitations

Ledger coverage is one µarch (Apple M2, secondary) — the primary-platform x86 entries (Zen 4/5, Golden Cove) await registered hardware; no numbers are invented in the interim (Charter T2/T7). Tier B families land at M6, AVX-512 at M7, packaging at M8. K5 gather and K1/K2/K3 selectivity-flatness evidence remain hardware-gated deferrals from M4.

Migration notes

None required.