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Release v0.8.0 — Second machine, x86 verdicts, convenience surface, MinMaxSummary rename

Date: 2026-08-21 · Scope: the first cross-microarchitecture release (intel-coffee-lake joins apple-m2), the API-ergonomics surface (ADR-027), and the accumulated evidence-gated performance work. Release template per REQ-DOC-010. Contains a breaking rename under the 0.x rules (REQ-API-009): deprecated aliases keep old code compiling through 0.x.

Summary

Quiver's performance record is no longer a single-machine story: an Intel i9-9900K (Coffee Lake, AVX2) is registered with a complete committed run — 377 entries, zero CV rejections, every equal-ISA verdict pair present — and the runner grew the tooling that made that possible (--rerun-noisy, the x86 baseline fixes, PMU columns). On the API side, the external ergonomics review landed in full: a zero-cost convenience surface and the rename of the one actively misleading name. MSVC moved from "documented exclusions" to a fully passing suite, closing R-18.

Highlights

  • First complete x86 ledger run (intel-coffee-lake, run 20260805-f7b016f85d08): all eight K10 arith_guarded verdict pairs — checked_add AVX2 beats the autovectorized baseline 3.18×/2.62×, flat across overflow density (ADR-014 confirmed on a second ISA); saturating_add AVX2 loses (0.71×/0.85×) and is published per Charter T7.
  • AVX2 64-bit filter ~4× faster after fixing a per-nibble control-vector expansion; AVX2 now beats the equal-ISA baseline on 20/20 measured shapes (ledger-confirmed 2.46–2.84×).
  • K10 checked arithmetic on AVX2 1.3–1.7× faster and finally measurable: pinned-phase bench allocation (hugetlb arena) plus batched bitmap stores dissolved a CV 0.12–0.24 measurement pathology (#62/#63).
  • --rerun-noisy N: REQ-LEDGER-005's "excluded until rerun" implemented — rejected entries get fresh-process rerun passes with every attempt's evidence kept; maiden run recovered 8 entries (worst chain CV 0.1855 → 0.0029).
  • Convenience surface (ADR-027): all_valid, bitmap_bytes, batch_view/selection_view, validity defaults, no-validity overloads, range-in/span-out overloads returning the written subspan, CheckedSum + sum_checked. Zero-cost; every form forwards to an unchanged primitive.
  • Breaking rename: Sma<T> → MinMaxSummary<T>, compute_sma → compute_min_max (deprecated aliases through 0.x). Plus the aarch64 integer dense min/max delegation (~3.8× user gain) and narrow-compare evidence from the Apple M2 arc.
  • R-18 closed: exact MSVC checked-sum without __int128 (a real cross-platform divergence, fixed and differentially verified over 800k adversarial sequences), a working Windows guard-page harness, and Windows CI running the full suite with zero exclusions.

Completed milestones and requirements

Milestones: none. M0–M8 shipped previously; M9/M10 remain partial/deferred per their gate records (the multi-µarch inputs advanced — a second machine is registered — but the ≥3-ISA/≥5-µarch gates stay open).

Requirements completed or materially advanced by this release:

  • REQ-LEDGER-005 — the "excluded from publication until rerun" clause is now implemented (--rerun-noisy), not just enforced by exclusion (#65, #67).
  • REQ-BENCH-010 — every K10 arith_guarded equal-ISA verdict pair exists on x86 (#60, #62, #63).
  • REQ-BENCH-013 — fixed-layout school realized via the pinned-phase hugetlb bench arena (#63).
  • REQ-LEDGER-012 — second registered machine (intel-i9-9900k) with committed publishable runs (#56, #61, #68); coverage gate progress, not closure.
  • API-K6-003 — the MSVC checked-sum fallback now meets the exact-unrepresentability contract (R-18 closure, #49).
  • REQ-TEST-006 / REQ-MEM-008 — Windows guard-page harness actually allocates and protects (#49).
  • API-K6-004 — renamed to compute_min_max returning MinMaxSummary (ADR-027, #48).
  • API-CORE-002 (new, PRD 04 §3.6) — the convenience surface (#48).

Ledger changes

New machine intel-i9-9900k with runs 20260730-373ec8eec66b (superseded, kept append-only) and 20260805-f7b016f85d08 (377 entries, zero CV rejections). Apple M2 runs 20260710-*/20260711-* (narrow compare, dense min before/after, mask queries before/after). No methodology change: the CV gate stands (QLM-1); #66 records the QLM-2 proposal for a future revision.

ADR changes

ADR-027 added (convenience surface + rename; the fluent-DSL and owning-STL-layer alternatives recorded as rejected/deferred). ADR-006 amended (span/range forms confined to the convenience overlay). R-18 closed in the risk register; MSVC tier-2 status became a governance gate rather than a technical gap.

API changes

  • Breaking: the Sma/compute_sma rename (deprecated aliases provided; removed at v1.0).
  • Additive: the convenience surface. The buffer-oriented primitives are unchanged and remain span-free (ADR-006 amendment).
  • Migration: Sma<T> → MinMaxSummary<T>, compute_sma(...) → compute_min_max(...). Nothing else changed; results are bit-identical (the MSVC checked-sum fix corrects a divergence).

Validation

Full CI matrix green on the release SHA (four tier-1 compilers plus MSVC now at 128/128 with no exclusions). Dev suite includes the review's target pipeline verbatim, forwarding-equivalence tests, and the deprecated-alias compile check. The amalgamation drop-in regenerated and compile-run verified against the modernized README quickstart. Nightly coverage publishes to Codecov (informational).

Performance evidence

Two registered machines, every claim traced to committed entries: ledger/results/apple-m2/ (runs 20260710-*, 20260711-*) and ledger/results/intel-coffee-lake/ (run 20260805-f7b016f85d08, plus the superseded-but-kept 20260730-* per append-only rules). Family pages carry the qle: references. Claims remain per-microarchitecture: nothing here asserts universality beyond the machines measured.

Known limitations

  • Native AVX-512 performance remains unmeasured (no hardware; correctness continues under Intel SDE). The three-µarch coverage gate for v1.0 needs one more machine class (hardware coverage plan).
  • The Coffee Lake environment characterization surfaced an irreducible ~1-in-35 per-process slow latch (+21%) documented in #62; #66 proposes the principled QLM-2 successor to the CV gate.
  • The deprecated aliases warn under -Werror builds — migrate (two renames) or suppress -Wdeprecated-declarations locally until then.